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n55s0 16 16 m - bit low v oltage, serial mask rom with 50mhz spi bus interface p/n: pm1437 re v . 1. 1 , mar ., 20 10 1 general description the n55s0 16 is a 16 mbit ( 2 m bytes) serial mask rom accessed by a high speed serial peripheral interface . key fe a tures ? operating voltage ranges from 3.0v to 3.6v ? serial perip h eral interface compatible - mode 0 and 3 ? high p erformance: "fast read" mode at 50mhz and "normal read" at 20mhz ? low power consumption: 8ma for fast read mode or 4ma for normal read mode ? low standby current: 15ua pin description symbol description sclk serial clock si serial data input so s erial data output csb chip select holdb hold to pause the device without deselecting the device vcc power supply vss ground order inform a tion part no. speed grade n55s0 16 20ns commercial
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 2 6 nc 7 vss1 8 vss2 9 si 10 sclk 1 holdb 2 vcc1 3 vcc2 4 csb 5 so physical specific a tions chip size: 4286.0 x 2976.0 (um) pad size: 76 x 76 (um) die thickness: 725 15 (um) figure 1. die p ad loc a tions note: 1. the ic substrate should be connected to vss in pcb layout.
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 3 t able 1. p ad description order p ad - name x - coord y - coord 1 holdb - 1920.09 - 1348.72 2 vcc1 - 1649.20 - 1348.71 3 vcc2 - 1431.48 - 1348.71 4 csb 354.43 - 1348.71 5 so 797.48 - 1348.71 6 nc 1865.85 1350.00 7 vss1 1597.71 1350.15 8 vss2 1380.07 1350.15 9 si - 1609 .25 1350.00 10 sclk - 1848.82 1349.99
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 4 x - decoder memo r y organiz a tion the memory is organized as: - 2 m bytes block diagram address gene r ator memo r y ar r a y si data regist er y - decoder cs# hold # mode logic state machine sense ampl ifier output buf f er so sclk clo c k gene r ator
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 5 device oper a tion stand - by mode when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps in standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high - z. active mode when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. spi feature input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the di f ference of spi mode 0 and mode 3 is shown as figure 1. figure 1. spi modes supported cp ol cpha shift in shift out (spi mode 0) 0 (spi mode 3) 1 0 sclk 1 sclk si msb so msb note: cpol indicates clo ck polarity of spi maste r , cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which spi mode is supported.
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 6 hold fe a ture hold# pin signal goes low to hold any serial communications with the device. the operation of hold requires chip select(cs#) to stay low and starts on falling edge of hold# pin signal while serial clock (sclk) signal keeps to be low (if serial clock signal does not keep to be lo w , hold operation will not start until serial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while serial clock(sclk) signal keeps to be low( if serial clock signal does not keep to be lo w , hold operation will not e nd until serial clock being low), please refer to figure 2. figure 2. hold condition operation cs# sclk hold# hold conditi on (standar d) hold condition (non - standard) the serial data output (so) is a high impedance, that both serial dat a input (si) and serial clock (sclk) are "don't care" during the hold operation. if chip select (cs#) drives high during hold operation, it will reset the in - ternal logic of the device. t o re - start the communication with chip, the hold# must be kept as hi gh and cs# must be kept as lo w .
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 7 t able 1. command definition command set 1s t byt e code 2nd byte 3rd byte 4th byte 5th byte 6th byte rdid(read id) 9fh m a n u f a c t u r e r id memor y typ e id memory density id read (read data) 03h ad1 (a23 - a16) ad2 (a15 - a8) ad3 (a7 - a0) data out (d7 - d0) note 1 fast read 0bh ad1 (a23 - a16) ad2 (a15 - a8) ad3 (a7 - a0) dummy cycle data out (d7 - d0) notes: 1. n bytes are read out until cs# goes high. 2. it is not recommended to adopt any code not in the above c ommand definition table.
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 8 command description (1) read identification (rdid) the rdid instruction is for reading the manufacturer id of 1 - byte and is followed by device id of 2 - byte. the nuvoton manufacturer id is c2h, the memory type id is 05h as th e first - byte device id, and the individual device id of sec - ond - byte id is:1 5 h. the sequence of issuing rdid instruction is: cs# goes low - > sending rdid instruction code - > 24 - bits id data is sent out on so - > to end rdid operation which can use cs# to be high at any time during data out. (see figure 3) when cs# goes high, the device is at standby stage. t able of id definitions: rdid manufacturer id memory type memory density 9fh c2h 05h 1 5 h (2) read data bytes (read) the read instruction is fo r reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the first address byte can be at any location. the address is automatically increased to the next higher address a fter each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low - > sending read i nstruction code - > 3 - byte address is sen t o n s i - > dat a ou t o n so - > t o en d rea d operatio n whic h ca n us e cs # t o b e hig h a t an y tim e durin g dat a out . (se e figure 4) (3) read data bytes at higher speed ( f ast_read) the f ast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single f ast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing f ast_read instruction is: cs# goes low - > send f ast_read instruction code - > 3 - byte address is sent on si - > 1 - dummy byte address is sent on si - >data out on so - > to end f ast_read operation which can use cs# to be high at any time during data out. (see figure 5) while program /erase/ w rite status register cycle is in progress, f ast_read instruction is rejected without any im - pact on the program/erase/ w rite status register current cycle.
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 9 figure 3. read identification (rdid) sequence (command 9f) cs# sc lk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 command s i 9f high - z s o manufacturer identification 7 6 5 3 2 1 0 device identification 15 14 1 3 3 2 1 0 m sb msb figure 4. read data bytes (read) seq uence (command 03) cs# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 sclk comma nd 24 - bit address s i 0 3 high - z 23 22 21 3 2 1 0 msb data out 1 data out 2 so 7 6 5 4 3 msb 2 1 0 7
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 1 0 figure 5. read at higher speed ( f ast_read) sequence (command 0b) cs# sc lk 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 comma nd 24 bit address s i 0 b 23 22 21 3 2 1 0 high - z so c s# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 sclk dummy byte s i 7 6 5 4 3 2 1 so 0 data out 1 7 6 5 4 3 2 1 0 data out 2 7 6 5 4 3 2 1 0 7 m sb msb msb
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 1 1 electrical specific a tions absolute maximum r a tings r a ting v alue a mbient operating t emperature commercial grade 0 ? c to 70 ? c storage t emperature - 65 ? c to 150 ? c applied input v oltage - 0.6v to 4.0v applied output v oltage - 0.6v to 4.0v vcc to ground potential - 0.6v to 4.0v notice: 1. stress greater than those listed un der absolute maximum r a tings may cause permanent damage of the device. this is stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum rating conditions in long period of time may a f fect reliabilit y . 2. specifications contained within the following t able 2 and 3 are subjects to change. 3. durin g voltag e transitions , al l pin s ma y overshoo t vs s t o - 2.0 v an d vc c t o +2.0 v fo r period s u p t o 20ns , se e figur e 6,7 . f i g u r e 6 . m a x i m u m n e g a t i v e o v e r s h o o t w aveform f i g u r e 7 . m a x i m u m p o s i t i v e o v e r s h o o t w aveform v ss vss - 2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns ca p aci t ance t a = 25 ? c, f = 20 mhz symbol p arameter min. typ max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 1 2 figure 8. input test w a veforms and measurement level input timing re f e r ance l e v el output timing re f e r ance l e v el 0.8vcc 0 .7vcc a c measurement 0.5vcc 0.2vc c 0.3vcc l e v el note: the r ise and f all time of input pulse < 5ns figure 9. output loading device under test 2.7k ohm +3.3v cl 6.2k ohm diodes=in3064 or e q ui v alent the conditi on "cl=30pf" includes jig capacitance
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 1 3 t able 2. dc characteristics ( t emperature = 0 ? c to 70 ? c, vcc = 3.0v ~ 3.6v) symbol p arameter notes min. typ max. units test conditions isb1 vcc standby 1 15 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 8 ma f=50mhz , sclk=0.1vcc/0.9vcc, so=open 4 ma f=20mhz , sclk=0.1vcc/0.9vcc, so=open ili input load 1 ? 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage 1 ? 2 ua vcc = vcc max, vin = vcc or gnd vil input low v oltage - 0.5 0.3vcc v vol output low v oltage 0.4 v iol = 1.6ma vih input high v oltage 0.7vcc vcc+0.4 v voh output high v oltage vcc - 0.2 v ioh = - 100ua
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 1 4 t able 3. ac characteristics ( t emperature = 0 ? c to 70 ? c, vcc = 3.0v ~ 3.6v) symbol a lt. parameter min. t yp. max. unit fsclk fc cloc k frequenc y fo r f ast_read , rdi d commands d.c. 50 (condition:30pf) mhz frsclk fr clock frequency for read commands d.c. 20 mhz tch(1) tclh clock high t ime 9 ns tcl(1) tcll clock low t ime 9 ns tsl ch tcss cs# active setup t ime (relative to sclk) 5 ns tchsl cs# not active hold t ime (relative to sclk) 5 ns tdvch tdsu data in setup t ime 2 ns tchdx tdh data in hold t ime 5 ns tchsh cs# active hold t ime (relative to sclk) 5 ns tshch cs# not active setup t ime (relative to sclk) 5 ns tshsl tcsh cs# deselect t ime 100 ns tshqz(2) tdis output disable t ime 8 ns tclqv tv clock low to output v alid 8 ns tclqx tho output hold t ime 0 ns tclch(2) clock rise t ime (3) (peak to peak) 0.1 v/ns tchcl(2) clock fall t ime (3) (peak to peak) 0.1 v/ns thhqx(2) tlz hold to output low - z 8 ns thlqz(2) thz hold# to output high - z 8 ns thlch hold# setup t ime (relative to sclk) 5 ns tchhh hold# hold t ime (relative to sclk) 5 ns thh ch hold setup t ime (relative to sclk) 5 ns tchhl hold hold t ime (relative to sclk) 5 ns notes: (1). tch + tcl must be greater than or equal to 1/ fc. (2). the values in the table are guaranteed by characterization, not 100% tested in production. ( 3). indicated as a slew rate.
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 1 5 figure 10. input t iming tshsl cs# tch sl tslch tchsh tshch sclk tdvc h tchcl tch dx tclch si ms b lsb high - z so figure 1 1. output t iming c s# tch sc lk tclqv tc lqv tcl tshqz tcl qx tclqx s o lsb tqlqh tqhql si addr.lsb in
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 1 6 figure 12. hold t iming cs# t h l c h sc lk tchhl thhch t c h h h thl qz thhqx so hold# * si is "don't care" during hold operation. revision history versi on date substantial change s page a1 .0 oct . 2 0 08 initial release all a1 .1 mar . 2 010
N55S016 p/n: pm1437 re v . 1. 1 , ma r ., 20 10 1 7 important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usag e includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instrume nts, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, custome r shall indemnify the damages and liabilities thus incurred by nuvoton.

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